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| TECHNICAL DATA IW4053B Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS The IW4053B analog multiplexer/demultiplexer is digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-to-peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a V - VEE of up to 13 V can be controlled; for VCC - VEE level CC differences above 13V a VCC - GND of at least 4.5V is required). These multiplexer circuits dissipate extremely low quiescent power over the full VCC -GND and VCC - VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic "1"is present at the ENABLE input terminal all channels are off. The IW4053B is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an enable input. Each control input selects one of a pair of channels which are connected in a singlepole double-throw configuration. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4053BN Plastic DIP IW4053BD SOIC IZ4053B chip TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off FUNCTION TABLE Control Inputs Enable C L L L L L L L L L L L H H H H X Select B L L H H L L H H X A L H L H L H L H X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None X0 X1 X0 X1 X0 X1 X0 X1 ON Channels PIN 16 =VCC PIN 7 = VEE PIN 8 = GND L H H = high level L = low level X = don't care INTEGRAL 1 IW4053B MAXIMUM RATINGS * Symbol VCC VIN IIN PD Ptot Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SO Package) Value -0.5 to +20 -0.5 to VCC +0.5 10 500* 100 -65 to +150 260 1 Unit V V mA mW mW C C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 - for Plastic DIP from -55 to +100C, for SO Package from -55 to +65C. +Derating - Plastic DIP: - 12 mW/C from 100 to 125C SO Package: - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. INTEGRAL 2 IW4053B DC ELECTRICAL CHARACTERISTICS Digital Section VCC Symbol VIH Parameter Minimum High-Level Input Voltage, ChannelSelect or Enable Inputs Maximum Low -Level Input Voltage, ChannelSelect or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Test Conditions VIS=VCC thru 1k VEE=GND=0 IIS<2A on all OFF Chanels RL=1k to GND VIS=VCC thru 1k VEE=GND=0 IIS<2A on all OFF Chanels RL=1k to GND VIN=VCC or GND VEE=GND=0 V 5 10 15 5 10 15 18 Guaranteed Limit -55 C 3.5 7 11 1.5 3 4 0.1 25 C 3.5 7 11 1.5 3 4 0.1 125 C 3.5 7 11 1.5 3 4 1.0 Unit V VIL V IIN A ICC Channel Select = VCC or GND VEE=GND=0 5 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 A DC ELECTRICAL CHARACTERISTICS Analog Section VCC Symbol RON Parameter Maximum "ON" Resistance Test Conditions VEE=GND=0 VIS = GND to VCC VEE=GND=0 V 5 10 15 5 10 15 18 Guaranteed Limit -55 C 800 310 200 100 25 C 1050 400 240 10* 15* 5* 100 125 C 1150 550 320 1000 Unit RON Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off- Channel Leakage Current, Any One Channel Maximum Off- Channel Leakage Current, Common Channel IOFF VEE=GND=0 nA VEE=GND=0 18 100 100 1000 * - Typical Value INTEGRAL 3 IW4053B INTEGRAL 4 IW4053B AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=20.0 ns) VCC Symbol tPHL(tPLH) Parameter Maximum Propagation Delay , Analog Input to Analog Output (Figure 1) RL=200k, VEE=GND=0 Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 1) RL=200 k, VEE=GND=0 Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 2) RL=10 k VEE=GND=0 VEE=-5A, GND=0 tPZL2(tPZH2) Maximum Propagation Delay , Enable to Analog Output (Figure 2) RL=10 k VEE=GND=0 VEE=-10A, GND=0 tPLZ1(tPHZ1) Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 2) RL=10 k VEE=GND=0 VEE=-5A, GND=0 tPLZ2(tPHZ2) Maximum Propagation Delay , Enable to Analog Output (Figure 2) RL=1,0 k VEE=GND=0 VEE=-10A, GND=0 CIN CI/O Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance VEE=GND=-5V CIS COS Feedthrough CIOS 5 5 5 5* 9* 0.2* pF V 5 10 15 5 10 15 5 10 15 5 5 10 15 5 5 10 15 5 5 10 15 5 Guaranteed Limit -55 C 60 30 20 350 200 160 720 320 240 450 720 320 240 400 720 320 240 450 450 210 160 300 25 C 60 30 20 350 200 160 720 320 240 450 720 320 240 400 720 320 240 450 450 210 160 300 7.5 125 C 70 40 30 400 250 200 720 320 240 450 720 320 240 400 720 320 240 450 450 210 160 600 pF ns ns ns Unit ns tPHL1(tPLH1) ns tPZL1(tPZH1) ns INTEGRAL 5 IW4053B ADDITIONAL APPLICATION CHARACTERISTICS VCC Symbol Parameter Test Conditions V BW Maximum OnChannel Bandwidth or Minimum Frequency Response (-3db) VEE=GND=0 RL=1k 20 log(VOS/VIS)=-3db VOS at Common OUT/IN V VIS** Limits Typical Value Unit 25 C 10 2,5 30 MHz VOS at Any Channel f1 (-40db) Feedthrough Frequency (All Channels OFF) VEE=GND=0 RL=1k 20 log(VOS/VIS)=-40db VOS at Common OUT/IN VOS at Any Channel f2 (-40db) Signal Crosstalk Frequency VEE=GND=0 RL=1k 20 log(VOS/VIS)=-40db Between any 2 Sections : In Pin 2, Out Pin 14 In Pin 15, Out Pin 14 VEE=GND=0 fIS=1kHz sine wave VEE=GND=0, RL=10k*** tr,t f=20ns Square Wave 10 2,5 60 10 10 2,5 2,5 8 8 MHz 10 10 5 10 15 10 2,5 2,5 1 1,5 2,5 - 2.5 6 0.3 0.2 0.12 65 MHz % THD Total Harmonic Distortion Address-or Enable to Signal Crosstalk VAO/I mV (Peak) ** Peak-to-peak voltage symmetrical about (VCC-VEE)/2. *** Both ends of channel. INTEGRAL 6 IW4053B INPUT tPLH ANALOG OUT t TLH 50% VCC GND t PHL VCC GND t THL 50% 10% 90% Figure 1. Switching Waveforms tr ENABLE CHANNEL-SELECT 10% INPUT tPLZ tf 90% 50% 50% VCC GND t PZL 90% 10% VCC VOL VOH ANALOG OUT 90% 10% GND t PZH t PHZ Figure 2. Switching Waveforms EXPANDED LOGIC DIAGRAM IN / OUT Ucc 16 LOGIC LEVEL CONVERSION BINARY 1 OF 2 DECODERS WITH ENABLE 3 5 1 2 13 12 TG TG TG TG TG TG 4 OUT/IN 15 OUT/IN 14 OUT/IN A 11 B 10 C9 6 ENABLE 8 GND 7 VEE INTEGRAL 7 IW4053B CHIP PAD DIAGRAM 1.95 + 0.03 Chip marking 204053 15 14 1.8 + 0.03 16 13 12 11 10 09 08 01 03 02 (0,0) 04 05 06 07 Location of marking (mm): left lower corner x=1.361, y=1.592; right higher corner x=1.423, y=1.652. Chip thickness: 0.460.02mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Location (left lower corner), mm X Y 0.116 0.453 0.116 0.175 0.362 0.116 0.669 0.116 1.074 0.116 1.287 0.115 1.699 0.290 1.699 0.620 1.699 0.973 1.700 1.268 1.640 1.583 1.063 1.583 0.756 1.583 0.429 1.583 0.116 1.445 0.116 0.942 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per passivation layer INTEGRAL 8 |
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